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quad, serial - input 12- bit/10- bit dacs ad7398/ad7399 rev. c information furnishe d by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, m a 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2000C 2011 analog devices, inc. all rights reserved. features ad7398 12 -b it r esolution ad7399 10 -b it r esolution programmable p ower s hutdown single (3 v to 5 v) or d ual ( 5 v) s upply o peration 3-w ire , s erial spi ?-c ompatible i nterface internal p ower - on r eset double b uffered r egisters for s imultaneous m ultichan nel dac u pdate four s eparate r ail - to -r ail r eference i nputs thin p rofile , tssop- 16 p ackage a vailable low t empco : 1.5 ppm/c qualified for automotive applications applications automotive output v oltage s pan portable communications digitally c ontrolled c alib ration pc p eripherals functional block dia gram dac a dac a register input reg a dac b register input reg b dac c register input reg c dac d register input reg d serial register power on reset dac d dac c dac b 12/10 clk v out a v out b v out c v out d sdi v ss rs ldac v ref c v ref d gnd cs v dd v ref b v ref a ad7398/ad7399 02179-001 figure 1. general description the ad7398/ad7399 family of quad, 12 - bit/10 - bit, voltage output digital - to - analog converters (dacs) is designed to operate from a single 3 v to 5 v s upply or a dual 5 v supply. built with the analog devices, inc. robust cbcmos process, these monolithic dac s offer the user low cost with ease - of - use in single or dual - supply systems. the applied external reference , v ref , determines the full - scale output voltage. valid v ref values include v ss < v ref < v dd that result in a wide selection of full - scale outputs. for multiplying applications , ac inputs can be as large as 5 v p . a doubled - buffered se rial - data interface offers high speed, 3- wire, spi - and microc ontroller - compa tible inputs using serial data - in (sdi), clock (clk), and a chip - select ( cs ). a common level - sensitive , load - dac strobe ( ldac ) input allows simultaneous update of all dac outputs from previously loaded i np ut r egisters. additionally, an internal power - on reset forces the output voltage to zero at system turn on . an external asynchronous reset ( rs ) also forces all registers to the zero code state. a programmable power - shutdown feature reduce s powe r dissipation on unused dacs. both parts are offered in the same pinout , enabling users to select the appropriate resolution for their application without redesigning the layout. for 8 - bit resolution applications , see the pin - compatible ad7304 produ ct. the ad7398/ad7399 are specified over the extended industrial ( ?40c to +125c) temperature range. parts are available in 16- lead, wide body soic and ultracompact , thin , 1.1 mm tssop packages. 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0. 1 0.2 0.3 0.4 0 4096 3584 3072 2560 2048 1536 1024 512 dnl (lsb) code (decimal) 02179-002 v dd = +5v v ss = ?5v v ref = +2.5v t a = 25c figure 2. ad7398 dnl vs. code (t a = 25 c)
ad7398/ad7399 rev. c | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional blo ck diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificat ions ..................................................................................... 3 ad7398 12 - bit voltage output dac ........................................ 3 ad7399 10 - bit voltage output dac ........................................ 4 timing diagrams .......................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................ 7 input registers .................................................................................. 8 ad7398 serial input register data format .............................. 8 ad7399 serial input register data format .............................. 8 terminology ...................................................................................... 9 typical performance characteristics ........................................... 10 theory of operation ...................................................................... 14 dac operation .......................................................................... 14 opera tion with v ref equal to the supply ................................ 15 power supply sequencing ......................................................... 15 programmable power shutdown .............................................. 15 worst case accuracy ................................................................. 15 serial data interface ................................................................... 15 power - on reset .......................................................................... 16 microprocessor interfacing ....................................................... 16 applications information .............................................................. 18 staircase windows comparator ............................................... 18 programmable dac reference voltage .................................. 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 21 revision history 1/11 rev. b to rev. c added automotive model and information .............. throughout 12/09 r ev. a to rev. b c hanges to ordering guide .......................................................... 21 6/06 rev. 0 to rev. a updated format .................................................................. universal changes to table 1 ............................................................................ 3 cha nges to table 2 ............................................................................ 4 changes to ordering guide .......................................................... 21 11/00 revision 0: initial version
ad7398/ad7399 rev. c | page 3 of 24 specifications ad 7398 12- bit voltage output d ac v dd = 5 v, v ss = 0 v; or v dd = + 5 v, v ss = ? 5 v, v ref = +2.5 v, ? 40 c < t a < +125 c, unless otherwise noted. table 1. parameter symbol condition 3 v to 5 v 10% 5 v 10% unit static performance resolution 1 n 12 12 bits relative accuracy 2 inl 1.5 1.5 lsb max differential nonlinearity 2 dnl monotonic 1 1 lsb max zero - scale error v zse data = 000 h 7 2.5 mv max full - scale voltage error v fse data = fff h 2.5 2.5 mv max full - scale tempco 3 tcv fs 1.5 1.5 ppm/c typ reference input v ref in range 4 v ref 0/v dd v ss /v dd v min/max input resistance 5 r ref data = 555 h , w orst c ase 35 35 k typ 6 input capacitance 3 c ref 5 5 pf typ analog output output voltage range v out 0 to v ref 0 t o v ref v output current i out data = 800 h , v out = 4 lsb s 5 5 ma typ capacitive load 3 c l no o scillation 200 400 pf max logic inputs logic input low voltage v il v dd = 3 v 0.5 v max v dd = 5 v 0.8 0.8 v max logic input high voltage v ih clk o nly 80% v dd 4.0 v min 2.1 to 2.4 2.4 v min input leakage current i il 1 1 a max input capacitance 3 c il 10 10 pf m ax interface timing 3 , 7 clock frequency f clk 11 16.6 mhz max clock width high t ch 45 30 ns min clock width low t cl 45 30 ns min cs to clock set up t css 10 5 ns min clock to cs hold t csh 20 15 ns min load dac pulse width t ldac 45 30 ns min data setup t ds 15 10 ns min data hold t dh 10 5 ns min load setup to cs t lds 0 0 ns min load hold to cs t ldh 20 15 ns min ac characteristics output slew rate sr data = 000 h to fff h to 000 h 2 2 v/ s typ settling time 8 t s to 0.1% of f ull s cale 6 6 s typ shutdown recovery t sdr 6 6 s typ dac glitch q code 7ff h to 800 h to 7ff h 150 150 nvs typ digital feedthrough q df 15 15 nvs typ feedthrough v out /v ref v ref = 1 .5 v dc 1 v p - p, data = 000 h , f = 100 khz ?63 ?63 db typ
ad7398/ad7399 rev. c | page 4 of 2 4 parameter symbol condition 3 v to 5 v 10% 5 v 10% unit supply characteristics shutdown supply current i dd_sd no l oad 30/60 30/60 a typ/max positive supply current i dd v il = 0 v, n o l oad, ?40c < t a < +125c 1.5/2.8 1.6/3 ma typ/max i dd v il = 0 v, n o l oad, ?40c < t a < +85c 1.5/2.6 1.6/2.8 ma typ/max negative supply current i ss v il = 0 v, n o l oad 1.5/2.5 1.6/2.7 ma typ/max power dissipation p diss v il = 0 v, n o l oad 5 16 mw typ power supply sensitivity pss v dd = 5% 0.006 0.006 %/% max 1 one lsb = v ref /4096 v for the 12 - bit ad7398. 2 the first eight code s (000 h to 007 h ) ar e excluded from the linear ity error measurement in single - supply operation . 3 these parameters are guaranteed by design and not subject to production testing . 4 when v ref is connected to either the v dd or the v ss power supply , the corresponding v out voltage program s between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the v zse error specification. see additional information in the theory of operation section . 5 input resistance is code dependent . 6 typicals represent average read ings measured at 25 c. 7 a ll input control signals are specified with t r = t f = 2 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. 8 the settling time specification does not apply for negative going transitions within the last 3 lsbs of grou nd. ad 739 9 10- bit voltage output d ac v dd = 5 v, v ss = 0 v; or v dd = + 5 v, v ss = C 5 v; v ref = +2.5 v, ? 40 c < t a < +125 c, unless otherwise noted. table 2. parameter symbol condition 3 v to 5 v 10% 5 v 10% unit static performance resolution 1 n 10 10 bits relative accuracy 2 inl 1 1 lsb max differenti al nonlinearity 2 dnl monotonic 1 1 lsb max zero - scale error v zse data = 000 h 7 4 mv max full - scale voltage error v fse data = 3ff h 15 15 mv max full - scale tempco 3 tcv fs 1.5 1.5 ppm/c typ refe rence input v ref in range 4 v ref 0/v dd v ss /v dd v min/max input resistance 5 r ref data = 155 h , w orst c ase 40 40 k typ 6 input capacitance 3 c ref 5 5 pf typ analog output output voltage range v out 0 to v ref 0 to v ref v output current i out data = 200 h , v out = 1 lsb 5 5 ma typ capacitive load 3 c l no o scillation 200 400 pf max logic inputs logic input low voltage v il v dd = 3 v 0.5 v max v dd = 5 v 0.8 0.8 v max logic input high voltage v ih clk o nly 80% v dd 4.0 v min 2.1 to 2.4 2.4 v min in put leakage current i il 1 1 a max input capacitance 3 c il 10 10 pf max interface timing 3 , 7 clock frequency f clk 11 16.6 mhz max clock width high t ch 45 30 ns min clock width low t cl 45 30 ns min cs to clock setu p t css 10 5 ns min clock to cs hold t csh 20 15 ns min load dac pulse w idth t ldac 45 30 ns min data setup t ds 15 10 ns min data hold t dh 10 5 ns min load setup to cs t lds 0 0 ns min load hold to cs t ldh 20 15 ns min
ad7398/ad7399 rev. c | page 5 of 24 parameter symbol condition 3 v to 5 v 10% 5 v 10% unit ac characteristics output slew rate sr dat a = 000 h to 3ff h to 000 h 2 2 v/ s typ settling time 8 t s to 0.1% of f ull s cale 6 6 s typ shutdown recovery t sdr 6 6 s typ dac glitch q code 1ff h to 200 h to 1ff h 150 150 nvs typ digital feedthrough q df 15 15 nvs typ feedthrough v out /v ref v ref = 1.5 v dc + 1 v p - p, ?63 ?63 db typ d ata = 000 h , f = 100 khz supply characteristics shutdown supply current i dd_sd no l oad 30/60 30/60 a typ/max positive supply current i dd v il = 0 v, n o l oad , ?40 c < t a < +125 c 1.5/2.8 1.6/3 ma typ /max i dd v il = 0 v, n o l oad , ?40 c < t a < + 85c 1.5/2.6 1.6/2.8 ma typ/max negative supply current i ss v il = 0 v, n o l oad 1.5/2.5 1.6/2.7 ma typ/max power dissipation p diss v il = 0 v, n o l oad 5 16 mw typ power supply sensitivity pss v dd = 5% 0.006 0.006 %/% max 1 one lsb = v ref / 1024 v for the 1 0- bit ad739 9. 2 the first two co des (000 h and 001 h ) a re excluded from the linear ity error measurement in single - supply operation . 3 these parameters are guaranteed by design and not subject to production testing . 4 when v ref is connected to either the v dd or the v ss power supply , the corresponding v out voltage program s between ground and the supply voltage minus the offset voltage of the output buffer, which is the same as the v zse error specification. see additional discuss ion in the theory of operation section . 5 input resistance is code dependent . 6 typicals represent average readings measured at 25 c. 7 a ll input control signals are specified with t r = t f = 2 ns (10% to 90% of 3 v) and ti med from a voltage level of 1.5 v. 8 the settling time specification does not apply for negative going transitions within the last 3 lsbs of ground. timing diagrams sdi t css t ds t dh t ch t cl t csh t ldac t ldh sa sd a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clk in reg ld t lds cs ldac 02179-003 figure 3 . ad7398 timing diagram (ad7399 with sdi = 14 bits only) clk t ch t cl t csh t css t lds t ldh t lds t ldac t css 1/ f clk cs ldac 02179-004 figure 4 . continuous clock timing diagram
ad7398/ad7399 rev. c | page 6 of 24 absolute maximum rat ings table 3. parameter rating v dd to gnd ?0.3 v, +7 v v ss to gnd +0.3 v, ?7 v v ref to gnd v ss , v dd logic inputs to gnd ?0.3 v, +8 v v out to gnd v ss ? 0.3 v, v dd + 0.3 v i out short circuit to gnd 50 ma thermal resistance ( ja ) 16- lead soic _w package (r w-16) 158 c/w 16- lead tssop package (ru -16) 180 c/w maximum junction temperature (t j max) 150c package power dissipation (t j max C t a )/ ja operating temperature rang e ?40 c to +125 c storage temperature range ?65 c to +1 50c reflow solde ring peak temperature snpb 240c pb -free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7398/ad7399 rev. c | pag e 7 of 24 pin configuration and function descripti ons 02179-005 1 v out b 16 v out c 2 v out a 15 v out d 3 v ss 14 v dd 4 v ref a 13 v ref c 5 v ref b 12 v ref d 6 gnd 11 sdi 7 ldac 10 clk 8 rs 9 cs ad7398/ ad7399 top view (not to scale) figure 5. pin configuratio n table 4. pin function descriptions table 5. control logic truth tab le cs cl ldac serial shift register function input register function dac register h x h no e ffect no e ffect no e ffect l l h no e ffect no e ffect no e ffect l + h s hift register data a dvanced o ne b it latched no e ffe ct l h h no e ffect latc hed no e ffe ct + l/h h no e ffect updated with shift r egister c ontents no e ffect h x l no e ffect latched transparent h x + no e ffect latched latche d notes 1. + = positive logic transition; C = negative logic transition; x = dont care . 2. at power - on , both the i nput r egister and the dac r egister are loaded with all zeros. 3. during p ower s hutdown, reprogramming of any internal registers can take place, but the output amplifiers do not produce the new values until the part is taken out of s hutdown mode. 4. the ldac input is a level - sensitive input that controls the four dac registers. pin no. mnemonic description 1 v out b dac b voltage output. 2 v out a dac a voltage output. 3 v ss negative power supply input. specified ran ge of operation 0 v to ? 5.5 v. 4 v ref a dac a reference voltage input terminal. establishes dac a full - scale output voltage. pin can be tied to v dd pin or v ss pin. 5 v ref b dac b reference voltage input terminal. establishes dac b full - scale output voltage. pin can be tied to v dd pin or v ss pin. 6 gnd ground pin. 7 ldac load dac register strobe. level s ensitive a ctive l ow. transfers all i nput r egister data to dac registers. asyn chronous active low input. see table 5 for ope ration. 8 rs resets input and dac registers to all zero codes. shift r egister contents unchanged. 9 cs chip select. active l ow i nput. disables shift register loading wh en high. transfers s erial r egis ter d ata to t he i nput re gister when cs returns h igh. does not effect ldac operation. 10 clk schmitt triggered clock input . positive e dge c locks d ata into s hift r egister. 11 sdi serial data input. input data loads directly int o the shift register. 12 v ref d dac d reference voltage input terminal. establishes dac d full - scale output voltage. pin can be tied to v dd pin or v ss pin. 13 v ref c dac c reference voltage input terminal. establishes dac c full - scale output voltage. pin can be tied to v dd pin or v ss pin. 14 v dd positive power supply input. specified range of operation 3 v to 5 v 10%. 15 v out d dac d voltage output. 16 v out c dac c voltage output.
ad7398/ad7399 rev. c | page 8 of 24 input registers ad7398 serial input register data forma t data is loaded in the msb first format . msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sa sd a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 note bit position b14 and bit position b15 are the sd and sa power shutdown control bits. if sa is set to logic 1, all dacs are placed in the power shutdown mode. if sd is set to logi c 1, the address decoded by bit b12 and bit b13 (a0 and a1) dete rmine the dac channel that is placed in the power shutdown state. ad7399 serial input register data format data is loaded in the msb first f ormat . msb lsb b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 sa sd a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 note bit position b12 and bit position b13 are the sd and sa power shutdown con trol bits . if sa is set to logic 1, all dacs are placed in the power shutdown mode. if sd is set to logi c 1, the address decoded by bit b10 and bit b11 (a0 and a1) determ ine the dac channel that is placed in the power shutdown state. table 6. ad7398/ad7399 address decode control sa sd a1 a0 dac channel affected 1 x x x all dacs s hutdown 0 1 0 0 dac a s hutdown 0 1 0 1 dac b s hutdown 0 1 1 0 dac c s hutdown 0 1 1 1 dac d s hutdown 0 0 0 0 dac a i np ut r egister d ecoded 0 0 0 1 dac b i nput r egister d ecoded 0 0 1 0 dac c i nput r egister d ecoded 0 0 1 1 dac d i nput re gister d ecoded
ad7398/ad7399 rev. c | pag e 9 of 24 terminology relative accuracy ( inl ) for the dac, relative accuracy or integral nonlinearity (inl) is a measur e of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. figure 6 illustrates a typical inl vs. code plot. differential nonlinearity ( dnl ) differential nonlinear ity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. figure 8 illustrates a typical dnl vs. code plot. zero - scale error (v zse ) zero - scale error is a measure of the output voltage error from zero voltage when zero code is loaded to the dac register. full - scale error ( v fse ) full - scale error is a measure of the output voltage error from full -scale volta ge when full - scale code is loaded to the dac register. full - scale temperature coefficient ( tc vfs ) this is a measure of the change in full - scale error with a change in temperature. it is expressed in ppm/ c or mv/ c. dac glitch impulse ( q) digital - to - analo g glitch impulse is the impulse injected into the analog output when the input code in the dac register changes st ate. it is normally specified as the area of the glitch in nv ? s and is measured when the dig ital input code is changed by 1 lsb at the major carry transition (midscale transition). a plot of the glitch impulse is shown in figure 15 . digital feedthrough ( q df ) digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. cs power supply sensitivity ( pss ) is held high while the clk and sdi signals are toggle d. it is specified in nv ? s, and is measured with a full - scale co de change on the data bus, such as from all 0s to all 1s and vice versa. a typical plot of digital feedthrough is shown in figure 16 . this specification indi cates how the output of the dac is affected by changes in the power supply voltage. power supply s ensitivity is quoted in terms of % change in output per % change in v dd for full - scale output of the dac. v dd is varied by 10%. reference feedthrough ( v out /v ref ) this is a measure of the feedthrough from the v ref input to the dac output when the dac is l oaded with all 0s. a 100 khz, 1 v p - p is applied to v ref . reference feedthrough is expressed in db or mv p - p.
ad7398/ad7399 rev. c | page 10 of 24 typical performance characteristics 1.50 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 0 4096 3584 3072 2560 2048 1536 1024 512 inl (lsb) code (decimal) 02179-006 ad7398 v dd = +5v v ss = ?5v v ref = +2.5v t a = 25c figure 6 . ad7398 inl vs. code (t a = 25 c) ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 inl (lsb) code (decimal) dac d t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 inl (lsb) code (decimal) dac c t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 inl (lsb) code (decimal) dac b t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v 02179-007 ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 inl (lsb) code (decimal) dac a t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v figure 7 . ad7399 inl vs. code (t a = 25c) 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0 4096 3584 3072 2560 2048 1536 1024 512 dnl (lsb) code (decimal) 02179-008 ad7398 v dd = +5v v ss = ?5v v ref = +2.5v t a = 25c figure 8 . ad7398 dnl vs. code (t a = 25 c) ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 dnl (lsb) code (decimal) dac d t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 dnl (lsb) code (decimal) dac c t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 dnl (lsb) code (decimal) dac b t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v 02179-009 ?0.50 ?0.25 0 0.25 0.50 0 128 256 384 512 640 768 896 1024 dnl (lsb) code (decimal) dac a t a = 25c, v dd = +5v, v ss = ?5v, v ref = +2.5v figure 9 . ad7399 dnl vs . code (t a = 25 c)
ad7398/ad7399 rev. c | pag e 11 of 24 1.00 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 inl, dnl, fse (lsb) reference voltage (v) 02179-010 inl dnl fse ad7398 t a = 25c v dd = +5v v ss = ?5v figure 10 . ad7398 inl, dnl, fse vs. reference voltage 100 90 80 70 60 50 40 30 20 10 0 0 4096 3584 3072 2560 2048 1536 1024 512 reference input current (a) code (decimal) 02179-011 ad7398 v dd = +5v v ss = ?5v v ref = +2.5v t a = 25c figure 11 . ad7398 reference input current vs. code 1000 100 10 0 4096 3584 3072 2560 2048 1536 1024 512 reference input resistance (k ?) code (decimal) 02179-012 ad7398 v dd = +5v v ss = ?5v t a = 25c figure 12 . ad7398 reference input resistance vs. code 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?20 201510 50 ?5 ?15 ?15 v out (mv) source or sink current from v out (ma) 02179-013 ad7398/ad7399 t a = 25c sinking current into v out v dd = +3v, v ss = 0v v dd = +5v, v ss = ?5v v dd = +5v, v ss = 0v sourcing current from v out v dd = +5v, v ss = ?5v v dd = +5v, v ss = 0v v dd = +3v, v ss = 0v figure 13 . v out vs. load current 25 20 15 10 5 0 0.4 2.62.42.22.01.81.61.41.21.00.80.6 counts full-scale error tempco (ppm/c) 02179-014 ad7398 sample size = 125 ?40c to +125c figure 14 . ad7398 full - scale error tempco time (2s/div) v out (0.2v/div) cs (5v/div) 02179-015 100 90 10 0% figure 15 . ad7398 midscale glitch
ad7398/ad7399 rev. c | page 12 of 24 02179-016 time (100ns/div) clock (5v/div) v out (50mv/div) 100 90 10 0% figure 16 . ad7398 digital feedthrough 02179-017 time (5s/div) cs (5v/div) v out (2v/div) dly 54s 5v 5s 2v 100 90 10 0% v dd = +5v, v ss = ?5v, v ref = +5v figure 17 . ad7398 large signal settling time 02179-018 time (2s/div) v dd = +5v, v ss = ?5v, v ref = +5v v out (2v/div) dly 67s a2 0.8v 5v 2s cs (5v/div) 2v 100 90 10 0% figure 18 . ad7398 shutdown recovery 100 1m 100k 0 ?108 ?96 ?84 ?72 ?60 ?48 ?36 ?24 ?12 10k 1k frequency (hz) attenuation (db) 02179-019 0x000 0x001 0x002 0x004 0x008 0x010 0x020 0x040 0x080 0x100 0x200 0x400 0x800 0x fff v dd = +5v v ss = ?5v v ref = +100mv rms t a = 25c figure 19 . ad7398 multiplying gain vs. frequency 5 2 1 6 5 0 1 2 3 4 1k 10k 100k 1m 10m 100m supply current (ma) clock frequency (hz) 02179-020 4 3 t a = 25c 1. v dd = +5v, v ss = ?5v, code = 0x000, 0xfff 3. v dd = +5v, v ss = ?5v, code = 0x555 3. v dd = +5v, v ss = 0v, code = 0x000, 0xfff 4. v dd = +5v, v ss = 0v, code = 0x555 5. v dd = +3v, v ss = 0v, code = 0x000, 0xfff 6. v dd = +3v, v ss = 0v, code = 0x555 figure 20 . ad7398 supply current vs. clock frequency 2.00 ad7398 t a = 25c v ref = +2.5v 1.00 1.25 1.50 1.75 2 3 4 5 6 power supply current (ma) power supply voltage (v) 02179-021 dual supply 3v 5v single supply figure 21 . ad7398 supply current vs. supply voltage
ad7398/ad7399 rev. c | pag e 13 of 24 3.0 0 0.5 1.0 1.5 2.0 2.5 ?50 0 50 100 150 supply current (ma) temperature (c) 02179-022 ad7398/ad7399 v dd = +5v v ss = ?5v figure 22 . supply current vs. temperature 36 35 34 33 32 31 ?60 ?40 14012010080604020 0 ?20 shutdown current (a) temperature (c) 02179-023 ad7398/ad7399 v dd = +5v v ss = ?5v figure 23 . shu tdown current vs. temperature 1.00 0.75 0.50 0.25 0 0 600 500 400 300 200 100 nominal change in voltage (mv) hours of operation at 150c 02179-024 ad7398 sample size = 135 v ref = 2.5v code = 0x fff code = 0x000 figure 24 . ad7398 long - term drift
ad7398/ad7399 rev. c | page 14 of 24 theory of operation 0 2179-025 v ref a v dd v ref b v ref c v ref d dac a dac register input register v out a dac b dac register input register v out b dac c dac register input register v out c dac d dac register input register v out d serial register clk sdi cs ad7398/ad7399 power on reset v ss gnd rs ldac address decode 4 12/10 figure 25. simplified block diagram the ad7398/ad7399 contain four 12-bit and 10-bit, respectively, voltage output, digital-to-analog converters. each dac has its own independent multiplying reference input. both the ad7398 and ad7399 use a 3-wire, spi-compatible serial data interface, with an asynchronous rs pin for zero-scale reset. in addition, an ldac strobe enables four-channel simultaneous updates for hardware-synchronized output voltage changes. 02179-026 ad7398/ad7399 v out a v ref gnd v ss v dd r r figure 26. simplified dac channel dac operation the internal r-2r ladder of the ad7398/ad7399 operates in the voltage switching mode, maintaining an output voltage that is the same polarity as the input reference voltage. a proprietary scaling technique is used to attenuate the input reference voltage in the dac. the output buffer amplifies the internal dac output to achieve a v ref to v out gain of unity. the nominal dac output voltage is determined by the externally applied v ref and the digital data (d) as v out = v ref d /4096 (for ad7398) (1) v out = v ref d /1024 (for ad7399) (2) where: d is the 12-bit or 10-bit decimal equivalent of the data word. v ref is the externally applied reference voltage. in order to maintain good analog performance, the user should bypass power supplies with 0.01 f ceramic capacitors (mount them close to the supply pins) and 1 f to 10 f tantalum capacitors in parallel. in addition, clean power supplies with low ripple voltage capability should be used. switching power supplies can be used for this application, but beware of its higher ripple voltage and pss frequency-dependent characteristics. it is also best to supply power to the ad7398/ad7399 from the systems analog supply voltages. do not use the digital 5 v supply. the reference input resistance is code dependent, exhibiting worst case 35 k for ad7398 when the dac is loaded with alternating codes 010101010101. similarly, the reference input resistance is 40 k for ad7399 when the dac is loaded with 0101010101.
ad7398/ad7399 rev. c | page 15 of 24 operation with v ref equal to the supply the ad7398/ad7399 are designed to approach the full output voltage swing from ground to v dd or v ss . the maximum output swing is achieved when the corresponding v ref input pin is tied to the same power supply. this power supply should be low noise and low ripple, preferably operated by a suitable reference voltage source such as adr292 or ref02. the output swing is limited by the internal buffer offset voltage and the output drive current capability of the output stage. users should at least budget the v zse offset voltage as the closest the output voltage can get to either supply voltage under a no load condition. under a loaded output, degrade the headroom by a factor of 2 mv per 1 ma of load current. also note that the internal op amp has an offset voltage so that the first eight codes of ad7398 may not respond at the supply voltage or at ground until the internal dac voltage exceeds the offset voltage of the output buffers. similarly, the first two codes of ad7399 should not be used. power supply sequencing v dd /v ss of ad7398/ad7399 should be powered from the system analog supplies. the external reference input can be supplied from the same supply to avoid a possible latch-up when the reference is powered on prior to v dd /v ss , or powered off subsequent to v dd /v ss . if v dd /v ss and v ref have separate power sources, ensure the power-up sequence is gnd, v dd , v ss , v ref /digital input/digital output. the reverse sequence applies to the power-down sequence. the order of v ref and digital input/digital output is not important. in addition, v ref pins of the unused dacs should be connected to gnd or some other power sources to ensure a similar power- up/power-down sequence. programmable power shutdown the two msbs of the serial input register, sa and sd, are used to program various shutdown modes. if sa is set to logic 1, all dacs are placed in shutdown mode. if sa = 0 and sd = 1, a corresponding dac is shutdown addressed by bit a0 and bit a1 (see the input registers section). worst case accuracy assuming a perfect reference, the worst-case output voltage can be calculated from the following equation: ?? inlvvv d v zse fse ref n out ????? 2 (3) where: d = decimal code loaded to dac ranges 0 d 2 n C1. n = number of bits. v ref = applied reference voltage. v fse = full-scale error in volts. v zse = zero-scale error in volts. inl = integral nonlinearity in volts. inl is 0 at full scale or zero scale. serial data interface the ad7398/ad7399 uses a 3-wire ( cs , sdi, clk) spi- compatible serial data interface. serial data of the ad7398 and ad7399 is clocked into the serial input register in a 16-bit and 14- bit data-word format, respectively. msbs are loaded first. the input registers section defines the 16 data-word bits for ad7398 and the 14 data-word bits for the ad7399. data is placed on the sdi pin, and clocked into the register on the positive clock edge of clk, subject to the data setup and data hold time requirements specified in the specifications section. data can only be clocked in while the cs chip select pin is active low. for the ad7398, only the last 16 bits clocked into the serial register are interrogated when the cs pin returns to the logic high state, and extra data bits are ignored. for the ad7399, only the last 14 bits clocked into the serial register are interrogated when the cs pin returns to the logic high state. because most microcontrollers output serial data is in eight-bit bytes, two right-justified data bytes can be written to the ad7398 and ad7399. keeping the cs line low between the first and second byte transfers results in a successful serial register update. once the data is properly aligned in the shift register, the positive edge of the cs initiates the transfer of new data to the target dac register, determined by the decoding of address bit a1 and address bit a0. for the ad7398, table 5, table 6, the input registers section, figure 3, and figure 4 define the characteristics of the serial interface. for the ad7399, table 5, table 6, the input registers section, and figure 4 (with a 14-bit exception) define the characteristics of the serial interface. figure 27 and figure 28 show the equivalent logic interface for the key digital control pins for ad7398 and ad7399. an asynchronous rs provides hardware control reset to zero- code state over the preset function and dac register loading. if this function is not needed, the rs pin can be tied to logic high. 02179-027 en clk sdi shift register address decoder a b c d cs to input register figure 27. equivalent logic interface
ad7398/ad7399 rev. c | page 16 of 24 power - on reset when the v dd power supply is turned on , an internal reset strobe forces all the i nput and dac registers to the zero - code state. the v dd power supply should have a smooth positive ramp without drooping in order to have consistent results, especially in the region of v dd = 1.5 v to 2.2 v. the v ss supply has no effect on the power - on reset per formance. the dac register data stay s at zero until a valid serial register data load takes place. esd protection circuits all logic input pins contain back - biased esd protection zeners connected to ground (gnd) and v dd as shown in figure 28 . 02179-028 gnd v dd digital inputs 5k? figure 28 . equivalent esd protection circuits microprocessor interfacing microprocessor interfacing to the ad7398/ad7399 is via a serial bus that uses standard protocol compatible with dsp processors and microcontrol lers. the communications channel requires a 3 - wire interface consisting of a clock signal, a data signal , and a synchronization signal. the ad7398/ad7399 req uire a 16 - bit/14 - bit data word with data valid on the rising edge of clk. the dac update can be don e automatically when all the data is clocked in, or it can be done under control of ldac . adsp - 2101 to ad7398/ad7399 interface figure 29 shows a serial interface between the ad7398/ad7399 and the adsp - 2101 . the a dsp - 2101 is set to operate in the serial p ort (sport ) transmit alternate framing mode. the adsp - 2101 is programmed through the sport control register and should be configured as follows: internal c lock o peration, a ctive l ow f raming, 16 -b it -w ord l ength. for the ad7398, transmiss ion is initiated by writing a word to the tx register after the sport has been enabled. for the ad7399, the first two bits are dont care as the ad7399 keep s the last 14 bits. similarly, transmission is initiated by writing a word to the tx register after the sport has been enabled. because of the edge - triggered difference, an inverter is required at the sclks between the dsp and the dac. 02179-029 ad7398/ ad7399 adsp-2101 1 fo ldac tfs cs dt sdi sclk clk 1 additional pins omitted for clarity. figure 29 . adsp - 2101 to ad7398/ad7399 interface 68hc11/68l11 to ad7398/ad7399 interface figure 30 shows a serial interface between the ad7398/ad7399 a nd the 68hc11/68l11 microcontroller. sck of the 68hc11 / 68l11 drives the clk of the dac, and the mosi output drives the serial data lines sdi. cs signal is driven from one of the port lines. the 68hc11 /68l11 are configured for master mode; mstr = 1, cpol = 0, and cpha = 0. data appearing on the mosi output is valid on the rising edge of sck. 02179-030 ad7398/ ad7399 68hc11/ 68l11 1 pc6 ldac pc7 cs mos1 sdi sck clk 1 additional pins omitted for clarity. figure 30 . 68hc1 1/ 68l11 to ad7398/ad7399 interface microwire ? to ad7398/ad7399 interface figure 31 shows an interface between the ad7398/ad7399 and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock and into the ad7398/ ad7399 on the rising edge of the serial clock. no glue logic is required as the dac clocks data into the input shift register on the rising edge. 02179-031 ad7398/ ad7399 microwire 1 so sdi sck clk 1 additional pins omitted for clarity. cs cs figure 31 . microwire to ad7398/ad7399 interface 80c51/80l51 to ad7398/ad7399 interface a serial interfac e between the ad7398/ad7399 and the 80c51/ 80l 51 microcontroller is shown in figure 32 . txd of the micro - controller drives the clk of the ad7398/ad7399, and rxd drives the serial data line of the dac. p3.3 is a bit - programma ble pi n on the serial port that is used to drive cs . 02179-032 ad7398/ ad7399 80c51/ 80l51 1 p3.4 ldac p3.3 cs rxd sdi txd clk 1 additional pins omitted for clarity. figure 32 . 80c51/80l51 to ad7398/ad7399 interface
ad7398/ad7399 rev. c | pag e 17 of 24 no te that the 80c51/80l51 provide the lsb first, although the ad7398/ad7399 expect the msb of the 16 - bit/14 - bit w ord first. care should be taken to ensure the transmit rou tine takes this into account. this can usually be done with software by shifting out and accumulating the bits in the correct order before inputting to the dac. in addition, 80c51 outputs two byte w ords/16 bits of data. t hus for ad7399, the first two bits, after rearrangement, should be d ont c are as they are dropped from the 14- bit word of the ad7399 . when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is valid on the falling edge of txd, so the clock must be inverted as the dac clocks data into the input shift register on the rising edge of the serial cloc k. the 80c51/80l51 transmit their data in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. as the ad7399 requires a 14- bit word, p3.3 (or any one of the other programmable bits) is the cs input signal to the dac; therefore p3.3 should be brought low at the beginning of the 16 - bit write cyc le 2 8 bit - words, and held low until the 16 - bit 2 8 cycle is completed. afte r that, p3.3 is brought high again and the new data loads to the dac. again, the first two bits, after rearranging, should be dont care. ldac on the ad7398/ad7399 can a lso be controlled by the 80c 51/ 80l51 serial port output by u sing another bit - programmable pin, p3.4.
ad7398/ad7399 rev. c | page 18 of 24 applications information staircase windows co mparator many applications need to determine whether voltage levels are within predetermined limits. some requirements are for nonoverl apping windows and others for overlapping windows. both circuit configurations are shown in figure 33 and figure 34, respectively . 02179-033 ad8564 10k? + ? + ? window 1 v+ 10k? + ? + ? window 2 v+ ad8564 10k? + ? + ? window 3 v+ 10k? + ? + ? window 4 v+ 1/2 ad8564 10k? + ? + ? window 5 v+ v test v ref ad7398/ ad7399 gnd v dd v out a v ref a v out b v ref b v out c v ref c v out d v ref d figure 33 . nonoverlapping windows comparat or 02179-034 v ref v out a v out b v out c v out d gnd window 2 window 1 window 3 window 4 window 5 figure 34 . nonoverlapping windows range 02179-035 ad8564 10k? + ? + ? window 1 v+ 10k ? + ? + ? window 2 v+ 1/2 ad8564 10k? + ? + ? window 3 v+ v test v ref ad7398/ ad7399 gnd v dd v out a v ref a v out b v ref b v out c v ref c v out d v ref d figure 35 . overlapping windows comparator 02179-036 v ref v out a v out b v out c v out d gnd window 1 window 2 window 3 figure 36 . overlapping windows range the nonoverlapping circuit employs one ad7398/ad7399 and t en comparators to achieve five voltage windows. these windows range between v ref and analog gro und as shown in figure 34. similarly, the overlapping circuit employs six comparators to achieve three overlapping windows (see figure 36 ).
ad7398/ad7399 rev. c | pag e 19 of 24 programmable d ac reference voltage with the flexibility of the ad7398/ad7399, one of the internal dacs can be used to control a common programmable v refx for the remainder of the dacs. the circuit configuration is s hown in figure 37 . the relationship of v refx to v ref is dependent upon the digital code and the rati o of r1 and r2, and is given by 1 2 2 1 2 1 r rd v r r vv n refx ref refx ? ? ? ? ? ? ? += (4 ) ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + = 1 2 2 1 1 2 1 r r n d r r v v ref refx (5 ) w here : d = d ecimal e quivalent of i nput c ode . n = number of b its . v ref = a pplied e xternal r eference . v refx = r eference v oltage for dac a to dac d. table 7 . v refx vs. r1 and r2 r1, r2 digital code v refx r1 = r2 0000 0000 0000 2 v ref r1 = r2 1000 0000 0000 1.3 v re f r1 = r2 1111 1111 1111 v ref r1 = 3r2 0000 0000 0000 4 v ref r1 = 3r2 1000 0000 0000 1.6 v ref r1 = 3r2 1111 1111 1111 v ref the accuracy of v refx is affected by the quality of r1 and r2 . therefore , tight tolerance , low tempco , thin film re sistors should be used. 02179-037 ad7398/ad7399 dac a v ref a v out a r1 0.1% r2 0.1% v ref vin dac b v ref b v out b adr293 dac c v ref c v out c dac d v ref d v out d to other components figure 37 . programmable dac reference
ad7398/ad7399 rev. c | page 20 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 38 . 16- lead standard small outlin e package [ soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches ) 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 39 . 16 - lead thin shrink small outline package [ tssop] (ru - 16) dim ensions shown in millimeters
ad7398/ad7399 rev. c | page 21 of 24 ordering guide model 1, 2 resolution (bits) temperature range package desc ription package option ordering quantity ad7398br 12 ?40c to +125c 16-lead soic_w rw-16 47 ad7398br-reel 12 ?40c to +125c 16-lead soic_w rw-16 1,000 ad7398brz 12 ?40c to +125c 16-lead soic_w rw-16 47 ad7398brz-reel 12 ?40c to +125c 16-lead soic_w rw-16 1,000 ad7398bru 12 ?40c to +125c 16-lead tssop ru-16 96 ad7398bru-reel7 12 ?40c to +125c 16-lead tssop ru-16 1,000 ad7398bruz 12 ?40c to +125c 16-lead tssop ru-16 96 ad7398bruz-reel7 12 ?40c to +125c 16-lead tssop ru-16 1,000 ad7398wbruz-rl7 12 ?40c to +125c 16-lead tssop ru-16 1,000 ad7399br 10 ?40c to +125c 16-lead soic_w rw-16 47 ad7399br-reel 10 ?40c to +125c 16-lead soic_w rw-16 1,000 ad7399brz 10 ?40c to +125c 16-lead soic_w rw-16 47 ad7399brz-reel 10 ?40c to +125c 16-lead soic_w rw-16 1,000 AD7399BRU 10 ?40c to +125c 16-lead tssop ru-16 96 AD7399BRU-reel7 10 ?40c to +125c 16-lead tssop ru-16 1,000 AD7399BRUz 10 ?40c to +125c 16-lead tssop ru-16 96 AD7399BRUz-reel7 10 ?40c to +125c 16-lead tssop ru-16 1,000 1 z = rohs compliant part. 2 w = qualified for auto motive applications. the ad7398 contains 3254 transistors. the di e size measures 1 08 mils 144 mils. automotive products the ad7398wbruz-rl7 model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that this automotive model may have specifications that differ from the commercial models; theref ore, designers should review the specifications section of this data sheet carefully. only the automotive grade product shown is ava ilable for use in automotive applications. contact your local analog devices account representative for specific product ordering informat ion and to obtain the specific automotive reliability reports for this model.
ad7398/ad7399 rev. c | page 22 of 24 notes
ad7398/ad7399 rev. c | pag e 23 of 24 notes
ad7398/ad7399 rev. c | page 24 of 24 notes ? 2000 C 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02179 -0- 1/11(c)

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